Reference is made to FIG. 1 showing a circuit diagram for a conventional image sensor pixel 10. The pixel 10 includes a photodiode 12 having an anode coupled to a first supply voltage node (Vsub; i.e., substrate voltage, for example, ground) 14 and a cathode coupled to a charge collection node 16. The photodiode 12 may, for example, be of a pinned photodiode type. An n-channel metal oxide semiconductor field effect transistor (MOSFET) 18, referred to as an anti-blooming transistor, has a source terminal coupled to the charge collection node 16 and a drain terminal coupled to a second supply voltage node (Vrt; i.e., a pixel reference voltage) 20. A gate terminal of the anti-blooming transistor 18 is coupled to receive an anti-blooming transistor control signal (Cab). An n-channel MOSFET 22, referred to as a transfer gate transistor, has a source terminal coupled to the charge collection node 16 and a drain terminal coupled to a sense node 24. A gate terminal of the transfer gate transistor 22 is coupled to receive a transfer gate control signal (Ctg). The sense node 24 is also known in the art as the floating diffusion node and has an associated parasitic capacitance. An n-channel MOSFET 26, referred to as a reset transistor, has a drain terminal coupled to a third supply voltage node (Vrst; i.e., a pixel reset voltage) 28 and a source terminal coupled to the sense node 24. The voltages Vrt and Vrst may or may not be at the same voltage potential depending on application. A gate terminal of the reset transistor 26 is coupled to receive a reset control signal (Crst). An n-channel MOSFET 30 has a gate terminal coupled to the sense node 24. The transistor 30 functions as a source-follower transistor. The drain terminal of source-follower transistor 30 is coupled to the second supply voltage node (Vrt) 20 while the source terminal is coupled to an intermediate (read) node 32. The voltage at the intermediate node 32 follows the voltage at the sense node 24. An n-channel MOSFET 34, referred to as a read transistor, has a drain terminal coupled to the intermediate node 32 and a source node coupled to an output line (VX) 36. A gate terminal of the read transistor 34 is coupled to receive a read control signal (Crd). In an embodiment where the pixel circuit 10 is part of a pixel array, the output line (VX) may be shared by plural pixels in a column of the array.
Reference is now additionally made to FIG. 2. The operation of the pixel 10 is as follows: The pixel 10 is first placed in reset mode. The anti-blooming transistor control signal (Cab) is asserted to turn on the anti-blooming transistor 18 (reference 70) and reset the photodiode 12. The reset control signal (Crst) is also asserted to turn on the reset transistor 26 (reference 72) and reset the sense node 24. The pixel 10 then enters an integration phase. The reset control signal (Crst) is deasserted to raise the corresponding potential barrier (reference 74). Light 40 is received by the photodiode 12 and photogenerated charges are produced (reference 76) in a charge collection region at the charge collection node 16. In the event that the light 40 is strong, or the integration time period is too long, excess photogenerated charges can be produced causing the cathode potential at charge collection node 16 to fall below the anode potential of the photodiode 12. In such a case, the photodiode 12 becomes forward biased and the excess charge will spill over to neighboring pixels. This effect is referred to in the art as “blooming.” To address this problem, the anti-blooming transistor control signal (Cab) is set at a voltage level that will slightly reduce the potential barrier presented by the anti-blooming transistor 18 (reference 78). In this configuration, the excess photogenerated charges instead pass (reference 80) to the drain terminal of the anti-blooming transistor 18. At the end of the integration phase, the pixel 10 enters the charge transfer phase. The anti-blooming transistor control signal (Cab) is deasserted to raise the corresponding potential barrier (reference 82). The transfer gate control signal (Ctg) is asserted to lower the corresponding potential barrier (reference 84) and the photogenerated charges are passed by the transfer gate transistor 22 to the sense node 24 (reference 86). The pixel 10 now enters the read out phase. The voltage potential on the sense node 24 is transferred to the intermediate (read) node 32 via the source-follower transistor 30. The read control signal (Crd) is asserted to turn on the read transistor 34 and transfer the voltage at the intermediate node 32 to the output line (VX) 36 (reference 88).
The operation of the pixel 10 in the manner described above can have an adverse effect on dynamic range. While the anti-blooming circuit and operation serves to address concerns with blooming, the photogenerated charges that are drained to the supply node 20 through the anti-blooming transistor 18 are lost and do not contribute at all to the signal that is read out to the output line (VX) 36.